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HIFI3 fixes for 17.0.1 release (LLVM-319) #89

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maciej-czekaj
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This PR contains the following fixes for pr #88 :

  • e89f8ed [Xtensa] Fix reg scavenging in XtensaRegisterInfo
  • 3dc2319 [Xtensa] Fix LLVM argument size for bool vectors.

Xtensa S3 DSP instructions are coded using explicit register allocation.
However, some instructions miss RegState:Define flag for output
registers. This leads MachineVerifier to raise errors.
This commit adds missing definitions.
Boolean Extension support consists of:
- v1i1 boolean vector type backed by BR boolean register class
- calling convection for boolean variables
- boolean instructions implementing logical operators
- truncation and zero-extension operations for conversion to scalars
- register spill and fill logic
loadImmediate is split into two functions:
- buildLoadImmediate which accepts allocated registers as params
- loadImmediate which allocates virtual registers

buildLoadImmediate is inteded to be used in post-RA passes.
BRegFixupPass implements post-RA transformations for boolean
instructions:
 - selecting the right constant for SLLI shift instruction based on
   physical register number. The number is unknown before regster
   allocation.
 - selecting the right constant for EXTUI bit extract operation based on
   physical BR register
 - emulating MOVBA (reg copy from AR to BR) operation
LLVM bitcode tests verify that Xtensa backend can:
 - convert between v1i1 and scalar
 - generate code for v1i1 vselect
 - spill & restore BR registers
 - load and store v1i1 values
Prepare a separate directory for Xtensa-specific Clang CodeGen tests.
Extend Xtensa C ABI test to include v1i1 parameters.
Adding __builtin_xtensa_movt_s and __builtin_xtensa_movf_s intrinsics.
Adding intrincic patterns to   MOVT_S anf MOVF_S definitions.
This patch adds a definition of Xtensa LX6 CPU variant present in Intel
Cannonlake and Tigerlake SOC platforms.
Some Xtensa targets may still use GAS as a default assemblwr through
-fno-integrated-as option. These changes make the assembly output
compatible with GAS by default.
  - GAS does not recognize .word but .2byte works for both
  - Dwarf CFI is not supported by GAS. Option -fdwarf-exceptions can
    still turn it on but there is no option to turn it off, so an
    opt-in approach is more portable.
Xtensa architecture uses v2i1 (BR2 reg class) and v4i1 (BR4 reg class) boolean vectors as arguments for HIFI instructions:
 - vector compare, e.g.: AE_EQ16X4
 - vector conditional move, e.g: AE_MOVT16X4
maciej-czekaj and others added 14 commits January 9, 2024 14:30
This option is passed to GNU AS and makes Xtensa compiler driver
compatible with GCC.
Intrinsics: __builtin_xtensa_ae_int32x2 and builtin_xtensa_int32
are convenience functions for easy integer-vector and vector-vector
conversions that conform to Xtensa coding style.
Xtensa C dialect allows for implicit conversion between wider and
narrower vector (via shuffle) and between integer and any vector (via
broadcast). Standard Clang vectors do not support this, so these
functions provide a handicap for better portability.
Commit d4f4b2f  [clang] Fix sizeof of boolean vector
changed the result of ASTContext::getTypeSize() for bool vector
to at least 8 bits. This commit fixes the Xtensa bool vector
size calculation.
Backward register scavenging (the only and default option now)
requires supportsBackwardScavenger() == true.
@github-actions github-actions bot changed the title HIFI3 fixes for 17.0.1 release HIFI3 fixes for 17.0.1 release (LLVM-319) Jan 15, 2024
@gerekon
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gerekon commented Jan 15, 2024

Ran pipelines

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gerekon commented Jan 16, 2024

@maciej-czekaj Looks like test on Windows fails

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gerekon commented Jan 17, 2024

@maciej-czekaj I merged GH PR pipeline #87. So you can rebase and drop DROPME: ... commits. All your pushes should run build/test pipeline automatically now.

@espressif-bot espressif-bot added Status: In Progress work is in progress and removed Status: Opened labels Jan 17, 2024
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gerekon commented Jan 19, 2024

@maciej-czekaj If you do not mind I will disable this test for Windows and merge this PR

@maciej-czekaj
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@gerekon I don't mind at all if you merge it by disabling Windows tests. Let's log a bug for that.

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gerekon commented Jan 24, 2024

merged

@gerekon gerekon closed this Jan 24, 2024
@espressif-bot espressif-bot added Status: Done Issue is done internally Resolution: Done and removed Status: In Progress work is in progress labels Jan 25, 2024
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3 participants