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SPI: one of the half-duplex modes is not supported #2687

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Tracked by #2494
bugadani opened this issue Dec 5, 2024 · 5 comments · Fixed by #2919
Closed
Tracked by #2494

SPI: one of the half-duplex modes is not supported #2687

bugadani opened this issue Dec 5, 2024 · 5 comments · Fixed by #2919
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@bugadani
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bugadani commented Dec 5, 2024

I can't actually tell whether the half-duplex mode we support is 3 or 4-wire single-bit. Our data modes are defined as:

#[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum SpiDataMode {
    /// `Single` Data Mode - 1 bit, 2 wires.
    Single,
    /// `Dual` Data Mode - 2 bit, 2 wires
    Dual,
    /// `Quad` Data Mode - 4 bit, 4 wires
    Quad,
    #[cfg(spi_octal)]
    /// `Octal` Data Mode - 8 bit, 8 wires
    Octal,
}

This suggests 4-wire half-duplex mode (MOSI, MISO both transfer data). This is essentially full-duplex with state machine control.

The ESP32 TRM explicitly calls out a different single-bit half-duplex mode:

The three-line half-duplex communication differs from four-line half-duplex communication in that the reception and transmission shares one signal bus

The other TRMs call out three-line half-duplex mode in a table, e.g. esp32-c6 v1.0 table 28-4.

Additionally, the hardware supports command/address/dummy phases in full-duplex transfer.


This is actually more general than the hardware supports (i.e. it's possible to generate invalid configuration). The set of options is roughly:

enum TransferMode {
    ThreeWireHalfDuplexSpi,
    FourWireHalfDuplexSpi,
    FullDuplexSpi,
    Qpi, // 4 bit command, address, data
    Opi, // 8 bit command, address, data
    WideSpiNarrowAddress(2/4/8 data bits), // 1 bit command, 1 bit address
    WideSpiWideAddress(2/4/8 data bits),   // 1 bit command, N bit address
}
@bugadani

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@tom-borcin tom-borcin added the investigation Not needed for 1.0, but don't know if we can support without breaking the driver. label Dec 18, 2024
@MabezDev MabezDev added this to the 1.0.0-beta.0 milestone Jan 6, 2025
@bjoernQ
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bjoernQ commented Jan 7, 2025

I think this boils down to just have a way to enable SIO

Easiest might be to just add a config option for that

@bugadani
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bugadani commented Jan 7, 2025

What would be the effect of that? Every half-duplex transfer would now be 3-wire, regardless of DataMode? Shouldn't SIO be configured on a per-transfer basis, so that we can support 4-wire half duplex on the same bus as 3-wire HD?

@bjoernQ
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bjoernQ commented Jan 7, 2025

Yes configuring it per transfer was the other option I thought about.

We shouldn't allow mixing any other DataMode with 3-wire mode in one transfer, then. Since those functions are fallible already, we can probably just check it and return a new error variant if needed

@bjoernQ
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bjoernQ commented Jan 9, 2025

I guess we reached consent here? (i.e. add a data mode for three-wire SPI)

If yes, I can assign this to me and remove the "investigation" label

@bjoernQ bjoernQ self-assigned this Jan 9, 2025
@bjoernQ bjoernQ removed the investigation Not needed for 1.0, but don't know if we can support without breaking the driver. label Jan 9, 2025
@bjoernQ bjoernQ mentioned this issue Jan 9, 2025
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@MabezDev MabezDev modified the milestones: 0.23, 1.0.0-beta.0 Jan 13, 2025
@github-project-automation github-project-automation bot moved this from Todo to Done in esp-rs Jan 17, 2025
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